The present invention relates to systems used to adjust the phase shift between the sampling clock and the data companion clock of an electronic chip adapted to receive data. In particular, the invention relates to a drift compensating system and method in a clock device of an electronic circuit.
High speed electronic circuits such as electronic chips widely used today, especially in telecommunication systems, are implementing electric interfaces consisting of a data and/or control high speed bus synchronized to one or more companion clocks provided at the interface according to various standards.
To properly process data or control signals, it is necessary for an electronic component receiving these signals as inputs to sample them appropriately at their input point. This is generally achieved using a training sequence during which the emitter component delivers a number of known training patterns on data/control signals while a receiver component controls and tunes its input sampling circuitry to properly recognize these patterns prior to switch to the operational mode.
Another technique to ensure optimum data sampling without requiring any data training sequence is illustrated in FIG. 1. A variety of implementations can be found depending on component manufacturer technology as well as low level design options or requirements. One implementation example is described in Xilin application note XAPP268.
In the implementation of FIG. 1, the data are received as parallel inputs by input receivers 10 and transmitted to the input flip-flops 12 which are clocked by the sampling clock signals received on inputs 14 which are provided by a clock phase alignment circuit.
The clock phase alignment circuit 16 is built around a clock management circuit 18 which has the property of acting like a phase locked loop circuit and provides one (or more) clock signal frequency locked to an input reference clock and whose phase is controlled with respect to the input reference clock. The latter is provided by the receiver 19 on input 20, used as a sampling clock for the data module as mentioned above. For this, the input clock drives an input flip-flop 21 (identical to data flip-flops 12) which is clocked by the output 22 and provides a sampled clock to control logic 24 which is typically a state machine. Control logic 24 monitors the sampled clock and permanently controls the clock management phase shift.
On startup (i.e. after the module reset), the phase shift of the clock management circuit 18 is set to a known predetermined value. The control logic 24 then examines the sampled clock output and evaluates it against a theoretical result (i.e., a bit to 1 or to 0) that should be obtained when sampled properly. The control logic 24 then alters the phase shift by one step or a small number of steps by sending either a phase advance or a phase delay to the clock management circuit 18. These evaluation/alteration operations are repeated as many times as necessary to determine a phase step validity window for which both input flip-flop setup and hold time are met to ensure a correct sampling. Once the window is determined, the control logic 24 asserts its “aligned” indicator 26 and the module can turn to the operational mode. Assuming an acceptable skew between the input data and the input clock and considering the close matching between devices in the same piece of silicon, the resulting alignment if suitable for the input clock signal is also suitable for data going across identical electronic structure.
In summary, the technique illustrated in FIG. 1 takes advantage of a clock signal to be a training sequence by nature and avoids using a specific data sequence. It ensures a clocking circuitry to match input flip-flop setup and hold time for proper input data sampling. Unfortunately, this system runs only once at startup time and then freezes the clock circuitry unless the whole system is started again. Furthermore, silicon timing characteristics may vary in time depending on environmental conditions (temperature, power, supply voltage, etc.), resulting in a drift which cannot ensure an optimum sampling.